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Virtuoso,analog
20nm
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Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in 10 minutes, Now What?
In my previous blogs , I talked about productivity enhancing features of Virtuoso Analog Design Environment XL and how designers can take advantage of these capabilities to design complex custom analog ICs. The Virtuoso Analog Design Environment XL multi-test bench environment, specification compliance...
Posted to
Custom IC Design
(Weblog)
by
Rama Jupalli
on Fri, Jul 29 2011
Q&A: How OpenText Provides Remote Access to Virtuoso
Since the Virtuoso custom/analog design environment is graphically intensive, you wouldn't expect it to run as well from a PC laptop in a hotel or foreign country as it does on a workstation. But that's the promise of Exceed OnDemand, a "managed application access solution" from Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 28 2011
User View: Bringing Digital Control Logic into Analog ICs
austriamicrosystems is an analog IDM that designs and manufactures ICs for applications such as power management, sensors, and sensor interfaces. But the company is not purely "analog." Most of its analog ICs have small amounts of digital control or bus interface logic, said Thomas Moerth,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 13 2011
How to Design Analog/Mixed Signal (AMS) at 28nm
Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Tue, Jun 21 2011
Virtuoso Analog Design Environment XL – Make Friends with Variation
In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity , I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use hardware resources efficiently. In this blog, I...
Posted to
Custom IC Design
(Weblog)
by
Rama Jupalli
on Thu, Jun 16 2011
DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions
Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 13 2011
Q&A: How ClioSoft Keeps IC Design Data Management “Simple”
IC design engineers want to spend their time designing, not managing files. Cadence Connections partner ClioSoft, a provider of hardware configuration management software, wants to keep it that way by providing easy-to-use tools that work seamlessly with IC design tools including the Cadence Virtuoso...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 26 2011
Virtuoso Analog Design Environment XL – Embrace the Productivity
In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote about the improvements in Open Access, SKILL and Virtuoso Schematic Editor in Virtuoso IC 6.1. In this blog, I am going to focus on Virtuoso Analog Design Environment, mainly on Virtuoso Analog Design Environment XL,...
Posted to
Custom IC Design
(Weblog)
by
Rama Jupalli
on Fri, May 6 2011
User View: Challenges and Solutions for Memory IP Development
Developing memory IP isn't easy - it's repetitive full-custom work that requires verification of many possible configurations. While full automation isn't possible, there are ways in which design tools and methodologies can make the task much easier. A recent conversation with engineers at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 20 2011
Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better
With the recent release of unified custom/analog flow that is based on the latest version of the Virtuoso IC 6.1.5 technologies (see Virtuoso IC 6.1.5 press release here ), it is time to revisit the strengths of Virtuoso IC 6.1 platform and find out how new capabilities enable designers with the productivity...
Posted to
Custom IC Design
(Weblog)
by
Rama Jupalli
on Wed, Apr 13 2011
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