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Virtuoso,UltraSim

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • Using AMS Ultrasim, clock input becomes triangular wave

    Hi! The simulator I'm using is AMS and the solver is Ultrasim. My clock generator is a Vsource from analog lib. At the first 55 cycles, the clock input is a square wave. After that it becomes a triangular wave. By any chance, is there some issue with the accuracy options of Ultrasim? Thanks!
    Posted to Cadence Academic Network (Forum) by eyec on Fri, Apr 26 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Differences between pins from digital and analog views of a schematic

    Hi, I have a mixed schematic, mostly analog but with some embedded digital controllers. The digital parts were made in SystemVerilog and imported into the correct views in virtuoso together with the schematics. Then using RC and Encounter the schematics and layout views were generated and also imported...
    Posted to Mixed-Signal Design (Forum) by glennramalho on Tue, Jan 22 2013
  • User Video and Presentation: Mixed-Signal Design Using OpenAccess

    A distinctive aspect of the Cadence Mixed-Signal Solution is the use of the OpenAccess database to integrate custom/analog (Virtuoso) with digital (Encounter Digital Implementation System) design. Embedded memory provider Spansion has given this methodology a thorough road test, as reported at the 2012...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 14 2013
  • Is Fast SPICE Simulation Hitting a Wall?

    The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed. So-called "Fast SPICE" simulators can provide considerable speedups -- but current Fast SPICE...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 19 2012
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: 5.10.41.500.6.137) within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
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