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Virtuoso,Circuit Design

  • High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

    Why high yield analysis? One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM core cell. It requires no fails in hundreds of millions...
    Posted to Custom IC Design (Weblog) by Hongzhou Liu on Mon, May 12 2014
  • What’s New in Virtuoso ADE XL in IC616 ISR6?

    In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3. Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6. Notes can be added to tests, variables...
    Posted to Custom IC Design (Weblog) by Tom Volden on Mon, Apr 28 2014
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Multi-VDD/Power-Gated Design VerilogIn

    Hi, Is there a way for the multiple-vdd and/or virtual vdd nets to be properly generated during verilogIn? The import process relies on using the schematic and symbol definitions from the artisan_cell library that is provided to us and any cells that we have power gated or supplied a lower vdd to in...
    Posted to Cadence Academic Network (Forum) by Northfork on Tue, Mar 26 2013
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Analog Design vs. Automation -- Why Are They At Odds?

    Back in 2002 and 2003 there was a lot of talk about analog synthesis being the "next new thing" to close the productivity gap between analog and digital designers. Well, I hope you didn't hold your breath for this! That promise failed mostly because analog design was still a custom design...
    Posted to Custom IC Design (Weblog) by Nigel on Tue, Aug 17 2010
  • Getting a Feel for RF

    It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine titled “ Getting some basic RF experience ”. I was surprising pleased that somebody took the time to talk about how one might get the feel for RF. That is because what Bob talks about is more or less...
    Posted to Custom IC Design (Weblog) by TomC on Wed, Apr 29 2009
  • Virtuoso Advanced Parallel Simulation Leveraging Parallelization Technology.

    There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager for Virtuoso APS that elaborates on parallelization technology and how it's been used to deliver improved performance in Virtuoso APS. Take a look, click here !
    Posted to Custom IC Design (Weblog) by deana on Tue, Feb 3 2009
  • So, where is that mixed-signal behavioral model I ordered?

    It has been said many time that SPICE, the analog engineers tool of choice, is virtually the same as it was 20 years ago, while digital engineers have been happily zooming up the evolutionary chain. There have been a number of attempts to prod analog designers into closing the gap with the introduction...
    Posted to Custom IC Design (Weblog) by Nigel on Sat, Jul 12 2008
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