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Virtuoso,Cadence,layout

  • User View: A 20nm Custom IC Constraint-Driven Flow

    If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 25 2012
  • Cadence crash !

    Hi, I have just installed a new PDK on my CADENCE IC 6.1.4, and I have the following errors that I cannot solve! : 1/ When I launch cadence IC6.1.4 with the command: "virtuoso", I can see in the CIW window that the initialization runs a lot of time and finally ends with : " * Error * unknown...
    Posted to Custom IC Design (Forum) by lraf on Fri, Aug 26 2011
  • Problem in layout with new cadence

    Hello, I am using the new cadence for the first time (IC6.1.5)and I am having a lot of problems with the layout (layout Suite L licence). One of the issues is that every time I create a new path. Once it is drawn, I cannot change its properties. Example: I create a M1 path of 0.5u width and I want to...
    Posted to Custom IC Design (Forum) by MariaOtz on Wed, May 4 2011
  • Filler Cells and Substrate Contacts in Virtuoso GXL

    Hi, I am using the student version of cadence tools at my Univ to auto place and route a custom design, using standard-cells. I am using the Custom IC tools suggested, i.e Schematic XL and Virtuoso GXL. I design the schematic of the architecture, first, then using the connectivity driven option, i generate...
    Posted to Custom IC Design (Forum) by nbtarun on Wed, Apr 7 2010
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