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  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • ADE window opens on opposite display

    Hi, I use Cygwin's X Server to access Cadence ADE L running on a linux machine. On my client there are 2 displays: 1 secondary (auxiliary) one to the left and a primary, main monitor on the right. Whenever ADE opens a new window, the new window appears always on the secondary monitor, in particular...
    Posted to Mixed-Signal Design (Forum) by itos on Mon, May 5 2014
  • VerilogA in AMS simulation: string parameter is not properly recognized

    Hi, I'm running a AMS Simulation using Cellview-based netlister and Spectre Solver. My simulation compiles fine when I configure all my cells to be only VerilogA. However, when I set the simulator to be AMS, Cellview-based netlister gives me the following error: file: /home/jorge/smdh/zr16_lp/analog...
    Posted to Mixed-Signal Design (Forum) by jsaenznoval on Mon, Feb 17 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Following are the details- 1) Comparator goes to unity feedback and then openloop - 222.22k 2) There are some caps and they either get connected b/w input of comparator and Supply or Input of comparator and ground- 2MHz 3) There is one switched cap BGREF. When comparator goes in unity feedback...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Re: Switched Cap based System Noise Analysis

    Hi Andrew, Thank you for being always first to answer. I referred your attachment before putting my query. But this says, it takes only one clock. In my system multiple switchings are happening and that too at different rates. Pardon my ignorance if I am not able to understand the material you attached...
    Posted to Mixed-Signal Design (Forum) by Abhishek D on Mon, Feb 10 2014
  • Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

    With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series. I know it's been a useful monthly exercise for me. Hopefully it has been helpful for everyone out there as well. Application Notes 1. How to Utilize a Windowing Technique...
    Posted to Custom IC Design (Weblog) by stacyw on Fri, Jan 17 2014
  • Spectre XPS – Cadence Reinvents FastSPICE Simulation

    Last year I wrote a blog post suggesting that FastSPICE simulation technology is "hitting the wall." A new approach is clearly needed, and Cadence is responding this week (Oct. 9, 2013) with Spectre XPS (eXtensive Partitioning Simulator), a FastSPICE simulator that sets new milestones for speed...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 9 2013
  • can we attach technology file to verilog-AMS design

    Hai all I am new to cadence and verilog-AMS i am trying to design ADC circuit completely in verilog-AMS description. i have a doubt that whether we can attach technology file(65nm or 180nm) to this design codes and get the power consumption of the circuit .if any one says yes we can then tell me how...
    Posted to Mixed-Signal Design (Forum) by sunilreddy on Fri, Aug 16 2013
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