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Virtuoso,ADE XL

  • Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online Support

    Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today. Application Notes 1. Cadence Online Support Release Highlights New features for searching and filtering, viewing cases and providing feedback 2. Generic Process Design Kit Downloads Get the latest versions...
    Posted to Custom IC Design (Weblog) by stacyw on Tue, Sep 2 2014
  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • What’s New in Virtuoso ADE XL in IC616 ISR6?

    In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3. Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6. Notes can be added to tests, variables...
    Posted to Custom IC Design (Weblog) by Tom Volden on Mon, Apr 28 2014
  • Efficient Design Migration Using Virtuoso Analog Design Environment GXL

    Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another. Additionally...
    Posted to Custom IC Design (Weblog) by Tom Volden on Fri, Mar 21 2014
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Archived Webinar: Variation-Aware Analysis for Advanced Node Design

    Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Nov 11 2012
  • Effect of load capacitor at the output of an oscillator

    Hi, While designing an oscillator ,which had a ring oscillator(differential ended) architecture , the frequency sensitivity of the vco had changed, that is if initially my vco works in a frequency range of 300MHz - 500MHz aor a control voltage range (1.3V-1.85V). After adding a capacitor at the output...
    Posted to Custom IC Design (Forum) by Jithin on Thu, Apr 12 2012
  • Running Cadence IC on VMware?

    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
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