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Virtuoso IC60,Virtuoso

  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Calculation of Sub Threshold and Gate Leakage Power

    Dear Sir, I am working on 6t SRAM cell and want to calculate Sub Threshold and Gate Leakage power of that. So please help me and tell me the steps to calculate the sub threshold and gate leakage power.
    Posted to Custom IC Design (Forum) by Shyam Akashe on Mon, May 30 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Cadence 6.1 problem

    Dear all, I know this might seem weird but it does happen to me.. I'm using cadence virtuso 6.1 for analog simulation. Sometimes I need the simulation to keep runing for the whole night, however, as soon as I leave it for some times, it just stops !!!, if return to my machine and start doing any...
    Posted to Custom IC Design (Forum) by Ayman Amin on Mon, Mar 29 2010
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