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  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • VerilogA in AMS simulation: string parameter is not properly recognized

    Hi, I'm running a AMS Simulation using Cellview-based netlister and Spectre Solver. My simulation compiles fine when I configure all my cells to be only VerilogA. However, when I set the simulator to be AMS, Cellview-based netlister gives me the following error: file: /home/jorge/smdh/zr16_lp/analog...
    Posted to Mixed-Signal Design (Forum) by jsaenznoval on Mon, Feb 17 2014

    I am new to AMS language and design and I am trying to model an oscillator with the following features : a. The oscillator operates at a default freq of say 32Khz, with tuning applicability from 20Khz to 50Khz. b. The oscillator operates in two power domains, one of 3.3v and other of 1.2v. c. When the...
    Posted to Mixed-Signal Design (Forum) by Sayantan55 on Sun, Sep 15 2013
  • Verilog-AMS Bias Current Modelling

    Hi All, I need to model a verilog-ams bias current model. I had coded in this way, I(out) <+ 1uA. In TB i put V(out) <+I(out)/R_LAOD. This worked fine at module level. Does this way of model works when the module connects with a SPICE block where the current is begin sinked. Is this the correct...
    Posted to Mixed-Signal Design (Forum) by shalem7 on Wed, Sep 4 2013
  • can we attach technology file to verilog-AMS design

    Hai all I am new to cadence and verilog-AMS i am trying to design ADC circuit completely in verilog-AMS description. i have a doubt that whether we can attach technology file(65nm or 180nm) to this design codes and get the power consumption of the circuit .if any one says yes we can then tell me how...
    Posted to Mixed-Signal Design (Forum) by sunilreddy on Fri, Aug 16 2013
  • Annotate veriloga or verilogams value on symbol

    Hi, I am interested in creating a symbol in Cadence which will have a label on it which is the value of a variable inside the verilog-a code of that block after a simulation has run. For instance, I have a "real" ron and I would like it's dc value to appear on my symbol. Thank you! Aaron
    Posted to Custom IC SKILL (Forum) by acook on Wed, Jul 10 2013
  • Re: about 64 - 32 bit binaries (ultrasim64)

    Dear Andrew, Thanks for your quick reply. Indeed I cannot run Ultrasim in 64bit mode. Below is the message I get: Connecting to License Server ... Done. Error found by UltraSim. ERROR (USIM-12701): The UltraSim-Verimix (mixed mode) simulator option is not compatible with 64-bit platforms. The UltraSim...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Fri, Jul 5 2013
  • about 64 - 32 bit binaries (ultrasim64)

    Hello, At the tool path "..../MMSIM101/tools/ultrasim/bin" I see the link to executable ultrasim64. However I have to exclude ultrasim from the 64bit tools in order to run (my machine is i5 and tools run on centOS). Is there a way to use 64bit binaries for ultrasim ? Another question: I use...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Wed, Jul 3 2013
  • Designing Digital FIR Filter using Cadence Tools

    Hello everyone, I am required to design FIR filter using Cadence tools for one of the projects that I am currently doing. I would like to mention that I am very new to this and have never done filter designing in cadence. Even have very minimal experience in Filter design in MATLAB. Thats why I am not...
    Posted to Mixed-Signal Design (Forum) by indra0804 on Wed, Jul 3 2013
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