Home > Community > Tags > Verilog
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Problem while running verilog-ams block in cadence schematic editor

    Hi, I am little bit new to the domain of verilog-ams. I have created blocks using verilog-a and have successfully simulated them along with other components like voltage sources, resistor etc. Now I am trying to create a block in verilog-ams that would convert logic to electrical signal and I would like...
    Posted to Custom IC Design (Forum) by indra0804 on Mon, Jul 8 2013
  • Need to place a pin on the symbol for an internal VerilogA signal

    I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal. So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic...
    Posted to Custom IC Design (Forum) by boast on Tue, May 7 2013
  • Verilog in and spice out procedure?

    Dear all, I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out. How does this process actually work? What are the tools I should use? Thank you so much!
    Posted to Digital Implementation (Forum) by rexnyu on Sat, Mar 30 2013
  • Error : Verilog-2001 feature.

    Dear all, I am trying to synthesize a design using RTL compiler (Version v07.10-p004_1 (32-bit), built Jun 18 2007). The tool gives the following error information: always @* begin | Error : Verilog-2001 feature. [VLOGPT-3] [read_hdl] : Implicit event expression in file 'gcm.v' on line 199, column...
    Posted to Logic Design (Forum) by rexnyu on Tue, Mar 26 2013
  • Improve Debug Productivity - SimVision Video Series on YouTube

    Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how SimVision can enable you to be much more productive in less than an hour after viewing the videos. Take...
    Posted to Functional Verification (Weblog) by Karnane on Tue, Feb 5 2013
  • RTL Compiler Hierarchical Flow

    Hello, Please, which is the manual that I must read to obatin the information on how to perform the hierarchical flow for RTL compiler synthesis ? Regards, Vitorio.
    Posted to Logic Design (Forum) by lvcargnini on Tue, Feb 5 2013
  • Handling rc/encounter generated pins in virtuoso

    Hi, I have been working with a digital block made in SystemVerilog and instantiated into a larger analog design. The HDL was imported into the corresponding cell views in virtuoso and symbols were generated for all hierarchical cells. After running synthesis and P&R the resulting netlist and layout...
    Posted to Mixed-Signal Design (Forum) by glennramalho on Wed, Jan 16 2013
  • IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

    EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 3 2012
  • Library for Verilog

    Hi, I have a question about creating symbol from verilog.v on vi editor. After finishing the codes and type :wq the following error occurs ncvlog: *W, DLCPH (/export_w19/umc130/cds.lib,4): cds. lib Invalid path ' /export_w19...../analogLib' (cds.lib command ignored). DEFINE cdsDefTechLib $CD_INST_DIR...
    Posted to Custom IC Design (Forum) by Cahe248 on Thu, Nov 15 2012
  • Re: How to get the activity power in Simvision

    Run a simulation (RTL or netlist) and dump your VCD file. In RTL Compiler: read the design (RTL or netlist, the same way as above. If VCD file is generated from RTL, read the RTL. If VCD file is generated from netlist, read netlist). elaborate the design. Then I will show another technique: call the...
    Posted to Functional Verification (Forum) by Sporadic Crash on Wed, Oct 24 2012
Page 2 of 5 (45 items) < Previous 1 2 3 4 5 Next >