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Verilog

Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...

Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012
Simulating verilog using cadence

Hi! I am new to this forum so please bear with me if my question is basic, anyways here goes. I am trying to simulate a state machine (kind of) in cadence using the ams simulator. NOw I have tested and verified that the design works using model sim. When I try to simulate it using the ams simulator the...

Posted to Logic Design (Forum) by MTP3 on Fri, May 11 2012
Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as 0x40000000, or 1 Gb. Thinking about a SystemC model...

Posted to System Design and Verification (Weblog) by jasona on Fri, Apr 13 2012
ncvlog: 10.20-s104

ncvlog: 10.20-s104: (c) Copyright 1995-2011 Cadence Design Systems, Inc. 7'd0 : Ival10u = -1.00E-05; | ncvlog: *E,EXPLPA (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/BP07_cinzia/BP07ZTCBIAS/verilogams/verilog.vams,68|15): e I need again help: //Verilog-AMS HDL for "BP07_cinzia"...

Posted to Functional Verification (Forum) by mrmzz on Thu, Mar 22 2012
Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I

I need a support for subject errr for a very simple code //Verilog-AMS HDL for "BP07", "BP07STARTUP" "verilogams" `include "constants.vams" `include "disciplines.vams" // Modification History : // Initial Release Mar 21 16:16:43 2012 // owner cici //...

Posted to Functional Verification (Forum) by mrmzz on Thu, Mar 22 2012
Webinar Report: Power-Aware Mixed-Signal Verification

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 19 2012
ncsim without any optimization

Hi, I want to run my behavioral model using ncsim without any optimization. I look at different option like -linedebug , -access +rwc but none will stop all the optimization like modelsim does with -novopt. Is there any equivalent option is NCSIM? I want to do this because my simulation is giving...

Posted to Functional Verification (Forum) by beatsonline on Fri, Nov 25 2011
Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here . (NOTE: This blog post was written by Walter Hartong...

Posted to Mixed-Signal Design (Weblog) by Paul Foster on Tue, Nov 1 2011
:)

Hello Everyone :)....;my name is Rupinder and i am btech final year student.Currently,i am using NC SIM. I just want to know about the latest simulator used in industries for logic design.

Posted to Functional Verification (Forum) by Rupinder on Wed, May 4 2011

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Verilog

Managing Inherited Connections with CPF in Virtuoso

Simulating verilog using cadence

Modeling Large Memories in SystemC

ncvlog: 10.20-s104

Beginner: ncvlog: *E,NOTSTT (/design/notebook/bp07/users/cinzia.cicchillitti+bp07+bp07a+41/cds5/BP07/BP07STARTUP/verilogams/verilog.vams,34|7): expecting a statement [9(I

Webinar Report: Power-Aware Mixed-Signal Verification

Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

ncsim without any optimization

Fred Discovers 1000x-10000x Speedup Using wreal Models

:)