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  • verilogin problem: modules are imported twice

    Hi All, I'm importing some verilog files into dfII library to generate a schematic to run a transistor level simulation.The library for standard cells are created first. When I use verilogin, it can proceed without errors but there is a weird problem, it will place each module twice, one with proper...
    Posted to Custom IC Design (Forum) by Howel on Tue, Aug 27 2013
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