Home > Community > Tags > Verilog/IC5141
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Verilog,IC5141

  • verilogin problem: modules are imported twice

    Hi All, I'm importing some verilog files into dfII library to generate a schematic to run a transistor level simulation.The library for standard cells are created first. When I use verilogin, it can proceed without errors but there is a weird problem, it will place each module twice, one with proper...
    Posted to Custom IC Design (Forum) by Howel on Tue, Aug 27 2013
Page 1 of 1 (1 items)