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Verilog-A,veriloga spectre

  • Re: model card vith a verilogA model through spectre

    Hello, In my case I am declaring new quantities (nature and discipline) in my veriloga file. I needed this to boost the value of the blowup in order to avoid some convergence problems I encountered. Now, I target to set my model card. using the lines : `include "disciplines.vams" //(* compact_module...
    Posted to Custom IC Design (Forum) by kjabeur on Wed, Jul 24 2013
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