will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > Verilog-A/veriloga cadence virtuoso 6.1.3 ADEL
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Verilog-A,veriloga cadence virtuoso 6.1.3 ADEL

  • Re: model card vith a verilogA model through spectre

    Hello, In my case I am declaring new quantities (nature and discipline) in my veriloga file. I needed this to boost the value of the blowup in order to avoid some convergence problems I encountered. Now, I target to set my model card. using the lines : `include "disciplines.vams" //(* compact_module...
    Posted to Custom IC Design (Forum) by kjabeur on Wed, Jul 24 2013
Page 1 of 1 (1 items)