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Verification

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 27 2013
SystemC sc_method schedule

Hi all, I have a question about systemC sc_method schedule. In my work, event A will trigger sc_method A, event B will trigger sc_method B; and sc_method A and B both will modify a same global variable. My question is what if event A and B happens at the same time? which sc_method will be scheduled first...

Posted to Hardware/Software Co-Development, Verification and Integration (Forum) by jxker on Sun, Feb 17 2013
IMC Exclusion Problem

Hey all, I am using IMC for my coverage .The problem is the tool automaticaly excludes some block coverage or expressions from the coverage.It shows "Exclusion Rule type : simulation time".Can someone explain what does Exclusion Rule typr mean and how do I remove it so that I can cover all...

Posted to Functional Verification (Forum) by Enginerd on Sun, Feb 10 2013
DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers

The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 24 2013
2013 CES: Top 4 Trends Benefiting EDA

While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Jan 17 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 9 2013
Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment

Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Tue, Jan 8 2013
Software-Driven Verification – a Hot Topic for 2013?

Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 3 2013

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Verification

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

SystemC sc_method schedule

IMC Exclusion Problem

DVCon 2013 for the Specmaniac

DVCon 2013 Preview – Learn from Other Design and Verification Engineers

2013 CES: Top 4 Trends Benefiting EDA

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment

Software-Driven Verification – a Hot Topic for 2013?