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SystemC sc_method schedule
Hi all, I have a question about systemC sc_method schedule. In my work, event A will trigger sc_method A, event B will trigger sc_method B; and sc_method A and B both will modify a same global variable. My question is what if event A and B happens at the same time? which sc_method will be scheduled first...
Posted to
Hardware/Software Co-Development, Verification and Integration
(Forum)
by
jxker
on Sun, Feb 17 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models
As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 17 2012
Free UVM Tutorial Boosts IC Functional Verification Skills
Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 12 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models
SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 13 2012
High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here . His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 26 2012
DAC 2012: High-Level Synthesis Tutorial Standing Room Only
Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing SystemC to Layout , led by Michael Bohm of Intel. The first session had over 100 attendees, standing room only: Later sessions each had over 50 attendees. The tutorial featured topics ranging from designing using...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 5 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification
On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...
Posted to
Functional Verification
(Weblog)
by
PeteHeller
on Tue, May 15 2012
In-Circuit Acceleration – A New IC Verification Use Model
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification use model called in-circuit acceleration....
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 15 2012
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