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Verification,Specman

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013

Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Mar 12 2013
DVCon 2013: Functional Verification Is EDA’s “Killer App”

With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event: DVCon 2013 was a one stop...

Posted to Functional Verification (Weblog) by jvh3 on Sun, Mar 10 2013
DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
Re: time between two events

you have sys.time and sys.realtime. You can log the time value when an event happens (using for example and on block) and next time you can calculate the delta. -hannes

Posted to Functional Verification (Forum) by hannes on Thu, Oct 11 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models

As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 17 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models

SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 13 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation

When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 2 2012

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Verification,Specman

Develop for Debugability – Part 1

Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013

DVCon 2013: Functional Verification Is EDA’s “Killer App”

DVCon 2013 for the Specmaniac

Re: time between two events

Webinar: New Interface Links Specman e Language to SystemC TLM Models

UVM Testflow Phases, Reset and Sequences

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Whitepaper: Connecting Specman e Language to SystemC TLM Models

User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation