	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Verification,FPGA

Place and route on SOC encounter

Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...

Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...

Posted to Industry Insights (Weblog) by rgoering on Fri, Mar 1 2013
DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 1 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Feb 23 2012
Q&A: GateRocket CEO Describes “Device Native” FPGA Verification and Debug

GateRocket is a Cadence Connections partner that focuses exclusively on verification and debugging solutions for complex FPGAs. The company's RocketDrive "device native" verification solution uses a real FPGA to complement simulation, providing both acceleration and debug visibility. In...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 24 2011
In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan." Even redo seems easier than to actually spend the time to write out a meaningful...

Posted to Functional Verification (Weblog) by Team MDV on Thu, Jan 13 2011
Acceleration And Emulation – Why HW/SW Integration Needs Both

Early software development on software virtual prototypes is a great capability, but at some point hardware/software integration requires the accuracy that only real hardware can bring. When that occurs, there are three choices - acceleration, emulation, and FPGA prototypes. Even though we are accustomed...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 26 2010

Page 1 of 1 (7 items)

Popular Tags

Email

Share

Subscribe

Contact Us

Verification,FPGA

Place and route on SOC encounter

DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Virtual Divide and Conquer Enables Fixed Sub-Systems

Q&A: GateRocket CEO Describes “Device Native” FPGA Verification and Debug

In Verification, Failing to Plan = Planning to Fail

Acceleration And Emulation – Why HW/SW Integration Needs Both