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Verification,ARM

Securing Invisible Things … or “Why Denial Works!”

The opening keynote of the Embedded World conference in Germany left me with chills. No, it was not a grand theatrical performance letting me crave for more. It simply scared the bejevies out of me with respect to the safety and security of embedded devices, some of which I use each day. Luckily -- as...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, Feb 27 2013
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 5 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 9 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 8 2012
ARM CTO at DAC 2012: The Truth About Semiconductor Scaling

As process nodes shrink, semiconductor scaling more or less follows the predictions of Moore's Law - but there are some surprising twists and turns. In a keynote speech at the Design Automation Conference ( DAC 2012 ) June 5, Mike Muller, co-founder and CTO of ARM, compared the original ARM1 processor...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 6 2012
12 Hot EDA Topics – 78 DAC Demo Sessions

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 24 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 7 2012
Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

I'm not proud to admit that I reacted with envy to the news that Twitter just received a $1 billion valuation . This story inspired further chatter claiming that if Twitter plays their cards right, they could achieve a $5 billion valuation before long. That's right: this fresh new internet combination...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Sep 23 2009
DAC Ecosystem Booth Panels Bring Out User Voice

At previous Design Automation Conferences, I’ve always been most interested in what EDA users have to say. One way to hear about the user experience at this year’s DAC is to attend any of five panels at the Cadence Ecosystem Partners booth (#4200, North Hall). These panels will include representatives...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 1 2009
Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.] At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title " Metric Driven Functional Verification of Embedded...

Posted to System Design and Verification (Weblog) by TeamESL on Mon, Mar 30 2009

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Verification,ARM

Securing Invisible Things … or “Why Denial Works!”

EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs

Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design

ARM CTO at DAC 2012: The Truth About Semiconductor Scaling

12 Hot EDA Topics – 78 DAC Demo Sessions

DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

DAC Ecosystem Booth Panels Bring Out User Voice

Software Verification or Validation With ISX?