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Verification methodology

  • The Increasingly Hazardous World of FPGA Verification

    Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, Oct 26 2010
  • A Quick Check on the Status of UVM 1.0

    Regular readers know that I've blogged a lot about the Open Verification Methodology (OVM) and the upcoming Accellera Universal Verification Methodology (UVM), whose 1.0 EA (Early Adopter) release is virtually identical to the OVM. I've been silent for a while, waiting for the Accellera VIP-TSC...
    Posted to Functional Verification (Weblog) by tomacadence on Thu, Sep 30 2010
  • e Templates: A Nifty Way To Create Reusable Code

    Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
  • Do Hardcopy Books Still Have Value?

    As my colleagues Adam Sherer and Joe Hupcey reported last week, Cadence has just published "A Practical Guide to Adopting the Universal Verification Methodology (UVM).” It is the world’s first book on the UVM. Or is it? The definition of "book" has become rather fuzzy these...
    Posted to Functional Verification (Weblog) by tomacadence on Thu, Jul 29 2010
  • Why The UVM Is Ready For Production Use Today -- Part 3

    This is the final installment of my blog posts based on the three common questions I heard at DAC regarding the Universal Verification Methodology (UVM). I've already answered the questions " What does the UVM mean for the future of the OVM and VMM? " and "Why is the first release...
    Posted to Functional Verification (Weblog) by tomacadence on Wed, Jul 7 2010
  • Tech Tip On Verification Environment Re-Use

    Verification has come a long way this past year, the highlight of which is UVM. UVM gives us verification productivity with testbench re-use because of a well defined SystemVerilog coding structure. But beyond UVM, what are the areas that are the most challenging and thus time consuming? We recently...
    Posted to Functional Verification (Weblog) by Team MDV on Mon, Jun 28 2010
  • A New Toy for UVM Geeks

    Wasn't it great when you were a kid at Christmas, and you got all those new toys to play with? You could keep yourself entertained for weeks, and with a really good toy, maybe the whole year. As we get older, our taste in toys changes, but the effect is still the same. My latest toy is my motorcycle;...
    Posted to Functional Verification (Weblog) by Team MDV on Fri, Jun 11 2010
  • UVM World Community Site Now Available!

    Yesterday morning, the verification world was buzzing with the first release of the Universal Verification Methodology (UVM) standard library and documentation from Accellera. This represents a major milestone for Accellera as well as for the EDA industry, since it is the first time that all the major...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, May 18 2010
  • Initial Release of the UVM Now Available!

    As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC) this morning posted the first release of the Universal Verification Methodology (UVM), tagged "1.0 Early Adopter" since there is a bit of new technology beyond the OVM 2.1.1 baseline. This is great news for the...
    Posted to Functional Verification (Weblog) by tomacadence on Mon, May 17 2010
  • What Does EDA360 Mean for Verification Engineers?

    I trust that most of you have seen the recent flurry of blog posts and articles about the new Cadence " EDA360 " vision. I was working on a blog entry on how this links to my world of verification when I saw my colleague Jack Erikson post " What Does EDA360 Mean for Logic Designers? "...
    Posted to Functional Verification (Weblog) by tomacadence on Mon, May 3 2010
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