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Verification methodology ,FPGA

  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • In Verification, Failing to Plan = Planning to Fail

    So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan." Even redo seems easier than to actually spend the time to write out a meaningful...
    Posted to Functional Verification (Weblog) by Team MDV on Thu, Jan 13 2011
  • The Increasingly Hazardous World of FPGA Verification

    Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification...
    Posted to Functional Verification (Weblog) by tomacadence on Tue, Oct 26 2010
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