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Verification methodology
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UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Mon, May 21 2012
UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"
To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Thu, May 3 2012
Formal Verification with Asynchronous Clocks
Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly varying clock phase timing parameters to cover the many possible combinations. A simple Verilog example...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Oct 13 2011
True Stories of Assertion Driven Simulation (ADS) in the Wild
Ever since Assertion-Driven Simulation (ADS) became available, I have been working with customers to integrate ADS into their standard design and verification flow. Below are some true stories from my direct experience with ADS out in the wilds of Silicon Valley. The very first use mode I helped a customer...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Jul 5 2011
Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal and ABV
To complement our support of DAC, CDNLive, and other large scale events, where the program touches on holistic approaches to whole levels of design and verification realization , Team Verify is also proud to host the "Club Formal" event series. Patterned after the popular "ClubT"...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Jun 28 2011
Video: Formal Verification Service Provider Oski Technology at DAC 2011
At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct increase in the level of interest in Formal and assertion-based verification (ref. my DAC report , and Tom's ). We weren't the only ones: at the Oski Technology booth (the same formal verification service provider...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Wed, Jun 22 2011
NEW Enterprise Planner Videos!
Videos on Enterprise Planner: What's it worth to you? Submitted By MDV Team Member - Paul Carzola Solutions Architect, Metric Driven Verification If a picture is worth a thousand words, then a video must be priceless -- at least I hope you think so. Recently, we created a few improvised videos on...
Posted to
Functional Verification
(Weblog)
by
Team MDV
on Tue, Apr 12 2011
In Verification, Failing to Plan = Planning to Fail
So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan." Even redo seems easier than to actually spend the time to write out a meaningful...
Posted to
Functional Verification
(Weblog)
by
Team MDV
on Thu, Jan 13 2011
New Interview with Partner Zocalo on Their Assertion Creation Philosophy and Approach for ABV
Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering just interviewed Zocalo president Howard Martin about assertion-based verification methodology -- including the dangers of an ad-hoc approach to ABV. To read the interview, click here . For some additional background...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Dec 9 2010
The Increasingly Hazardous World of FPGA Verification
Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Oct 26 2010
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