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  • Clone in new window

    Is there any option to open the Clone in new layout window, as I can do edit place only
    Posted to Custom IC SKILL (Forum) by Gurup on Wed, Jan 1 2014
  • Skill code to automatically map instances via name in layout xl

    Sometimes the layout instances don't map with the schematic (vxl clean) even if the lvs comes clean. I have to mannualy go to device correspondance & map them. Is there any skill code that can be used to map them when the layout xl fails to automatically map.
    Posted to Custom IC SKILL (Forum) by Deepon Saha on Thu, Nov 28 2013
  • to set a bind key to show/hide dummy/odummy

    I'd like to set a bind key to show/hide dummy/odummy, here is part of code: procedure(ST_Lyt_ShowHide_Layers(Command PressedKey ShowDummy) ;Available values for Command: >=1 to Add, <=1 to Remove and 0 to Hide all but selected one ;Available values for ShowDummy: t to show dummy types and nil...
    Posted to Custom IC SKILL (Forum) by Weight66 on Mon, Feb 18 2013
  • Re: stubborn VXL markers

    Hi Quek, There is no "Guides" view from the Window->Assistants menu. I'm assuming that lives in a later release of Cadence. I am on 6.1.4-64b.500.11. The Markers are Objects. In prior releases of Cadence I would turn them off thru the LSW->Object->Markers->Vis and Sel control...
    Posted to Custom IC Design (Forum) by linbo on Mon, Apr 30 2012
  • how to stop layout from turning into layout XL, 6.1.4

    Hi Folks, Here's a fairly new behavior that's been bugging me--I'm hoping someone can supply me with the setting to fix. At one point I had a cell in VXL. Layout/schematic. I've since "turned" VXL off (Launch->Layout L and Launch->Schematic L). Whenever I descend|edit...
    Posted to Custom IC Design (Forum) by linbo on Mon, Apr 2 2012
  • VXL layout links to schematic

    Dear All, As I am concerned I have not seen this point answered yet or I may not ask the correct question in the forum search. Using VXL flow, I am selecting a couple of ports in the layout and of course the corresponding selected ports are selected in the schematic. I am able to grab the list of selected...
    Posted to Custom IC SKILL (Forum) by frogconsultant on Thu, Oct 27 2011
  • VXL pin generation of inherited nets

    Dear all, I have already looked into Solution ID: 1833291 but it does not seem to help me. I would like to know how top level schematic nets that are 1. not connected to any pins ( in top level ) 2. inherited in lower level schematic( inherited connection) treated during VXL pin generation. I have a...
    Posted to Custom IC SKILL (Forum) by cmohan on Wed, Jul 27 2011
  • Illegal hierarchical connection

    I'm getting huge numbers of the message: Warning: Illegal hierarchical connection to internal net between instance...... I can't understand why these warning boxes are even there but so many?! Even when I'm connecting to the pin I still often get the warning box hassles. Why would Cadence...
    Posted to Custom IC Design (Forum) by MontyP on Thu, Jan 20 2011
  • VXL - forcing conectivity of existing nets

    Hi, I had a Designer do some modification to a layout I created. They basically reordered a few devices for better matching. Now I find that the devices have been renamed but the metal paths connecting them have the old names and VXL is refusing to enable the 'Show Incomplete Nets' functions...
    Posted to Custom IC Design (Forum) by DCrampton on Wed, May 27 2009
  • How to display a p-cell's constituent layers in a layout (Layout XL, Virtuoso IC6.1.1)

    In previous versions of Cadence Virtuoso, hitting the Shift+F key combination in Layout XL allowed me to display p-cells as sub-layouts with their constituent individual layers (that way I could easily find their pins and wire them to the rest of the layout), while hitting Ctrl+F would revert back to...
    Posted to Custom IC Design (Forum) by Unicode787Plus on Wed, Feb 25 2009
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