Home > Community > Tags > VHDL/rtl compiler
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

VHDL,rtl compiler

  • Re: Does clock power included in Power Report ?

    [quote user="grasshopper"] Hi dkhan, unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not...
    Posted to Logic Design (Forum) by dkhan on Mon, Jul 29 2013
  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • RTL compiler command for retaining design hierarchy

    Hi, Is there a command in RTL compiler which can force the synthesizer to retain original hierarchy of the design, like there is in Xilinx ISE for instance? Thanks.
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • using ModelSim/QuestaSim VCD file in RTL compiler

    Hi, I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports...
    Posted to Logic Design (Forum) by dkhan on Tue, Jun 18 2013
  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
Page 1 of 1 (6 items)