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  • Webinar: Is SystemVerilog the Future of Mixed-Signal Modeling?

    Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 4 2012
  • How to Simulate 64-bit VHDL Code in Cadence?

    I am trying to simulate a VHDL code which have internally values exceeds the range of (-2**31 to 2**31). However, I can synthesize the code but I can't simulate it. I tried to change the attribute set intovf_severity_level IGNORE but it didn't work as well. I would appreciate your suggestions...
    Posted to Logic Design (Forum) by shahein on Tue, Sep 4 2012
  • Synthsis of VHDL-2008 on RC

    Dear All, I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly. However, I am not able to synthesis the same code using RC. I am using Cadence 5 flow with RC v10.1. What is your recommendations to overcome this issue...
    Posted to Digital Implementation (Forum) by shahein on Thu, Jul 26 2012
  • Re: How will I do a HAL Hdl analysis on vhdl design?

    Hi Shivani. If you compile your design with "irun" already then you can just add the "-hal" switch, then use the "ncbrowse" tool to review the lint messages via a GUI. Alternatively if you use ncvhdl/ncelab/ncsim, then after elaboration you can invoke "hal" and...
  • Protected Data Types by VHDL 2008

    I am trying to compile some VHDL files which contains a protected data type . I am using Cadence 10.2 . I set the library path to the Incisive library path, i.e., $IUSHOME /tools/inca/files. In this folder I check the csd.lib file and the IEEE proposed library. The library is already compiled at the...
    Posted to Functional Verification (Forum) by shahein on Mon, May 14 2012
  • reg : vhdl design with systemverilog testbench

    Hi Everyone, Could someone help me in verifying "vhdl" design using systemverilog testbench , i am using INCISIVE 10.20.026 as "irun sample.vhd tb_sample.sv" and it is giving the following error " ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin function...
    Posted to Functional Verification (Forum) by Srikanth Madam on Thu, Jan 12 2012
  • NCSIM: problem with vcd filesize limit

    Hi, I'm currently working with a vhdl example to check the ability of ncsim to limit the filesize of vcd dumpfiles. For that I set up a simple mux with a testbench, that generates stimuli over 540ms. The following simulation flow results in a 1,7G VCD file: $ ncvhdl -cdslib ./cds.lib -hdlvar ./hdl...
    Posted to Functional Verification (Forum) by hbeck on Mon, Aug 22 2011
  • VHDL to schematic

    Hi, I'm using Allegro Design Entry CIS 16.3...and I'm wondering if it is possible to use a VHDL file that executes logic (Thermometer to binary), and create a hierarchical block with it that will work in simulation for an ADC I'm designing? I was able to create the VHDL file and then I placed...
    Posted to PCB Design (Forum) by DaveAJohnson on Wed, Apr 27 2011
  • UVM Meets SystemC and VHDL in DVCon “Town Hall” Forum

    Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 1 2011
  • C-to-Silicon

    Dear reader, For my PhD research I am currently comparing several C to VHDL/Silicon approaches and tools. We have set up a library of kernels and on this library we automatically run the DWARV c-to-vhdl compiler and the C-to-Verilog compiler from Israel. We were also considering doing the generation...
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