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VHDL

  • Protected Data Types by VHDL 2008
    I am trying to compile some VHDL files which contains a protected data type . I am using Cadence 10.2 . I set the library path to the Incisive library path, i.e., $IUSHOME /tools/inca/files. In this folder I check the csd.lib file and the IEEE proposed library. The library is already compiled at the...
    Posted to Functional Verification (Forum) by shahein on Mon, May 14 2012

  • reg : vhdl design with systemverilog testbench
    Hi Everyone, Could someone help me in verifying "vhdl" design using systemverilog testbench , i am using INCISIVE 10.20.026 as "irun sample.vhd tb_sample.sv" and it is giving the following error " ASSERT/WARNING (time 0 FS) from package ieee.STD_LOGIC_ARITH, this builtin function...
    Posted to Functional Verification (Forum) by Srikanth Madam on Thu, Jan 12 2012

  • NCSIM: problem with vcd filesize limit
    Hi, I'm currently working with a vhdl example to check the ability of ncsim to limit the filesize of vcd dumpfiles. For that I set up a simple mux with a testbench, that generates stimuli over 540ms. The following simulation flow results in a 1,7G VCD file: $ ncvhdl -cdslib ./cds.lib -hdlvar ./hdl...
    Posted to Functional Verification (Forum) by hbeck on Mon, Aug 22 2011

  • VHDL to schematic
    Hi, I'm using Allegro Design Entry CIS 16.3...and I'm wondering if it is possible to use a VHDL file that executes logic (Thermometer to binary), and create a hierarchical block with it that will work in simulation for an ADC I'm designing? I was able to create the VHDL file and then I placed...
    Posted to PCB Design (Forum) by DaveAJohnson on Wed, Apr 27 2011

  • UVM Meets SystemC and VHDL in DVCon “Town Hall” Forum
    Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 1 2011

  • C-to-Silicon

    Dear reader, For my PhD research I am currently comparing several C to VHDL/Silicon approaches and tools. We have set up a library of kernels and on this library we automatically run the DWARV c-to-vhdl compiler and the C-to-Verilog compiler from Israel. We were also considering doing the generation...
    Posted to System Design and Verification (Forum) by roel on Thu, Aug 19 2010

  • MixedLanguage (Verilog+VHDL) Question
    Hello: I am using ncsim 09.20-s016. I have a VHDL DUT. The testbench top level is VHDL. But, I have a few Verilog modules in the testbench. From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). For example, if (top.level_1.level_2.sigout_1 == 1'b1) $display("Posedge...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Aug 5 2010

  • DAC Report: Interview With AMIQ And Update On Their “DVT” IDE
    One of the benefits of the Design Automation Conference is the opportunity to follow the growth trajectory of partner companies with each successive show. Last year our long time Verification Alliance partner AMIQ ( a name familiar to many Specmaniacs ) made their first appearance at DAC, and they were...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Jun 30 2010

  • Specman, e, and EDA360
    The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward for Electronic Design" ; and for good reason - in 2010 the electronics world is finally starting to transform in ways that have been long anticipated by Specmaniacs and our "Trailblazer" program partners...
    Posted to Functional Verification (Weblog) by teamspecman on Tue, Jun 8 2010

  • Adam’s Verification Top 10 In '10
    I love top 10 lists. Not so much for the drama of the count-down, but for arguments that inevitably fall out of any prioritization. So here is my verification top 10 in '10, let the rants begin! 10. VHDL 1076-2009 Support . Huh? How did this get here? Given the breadth of IES (Incisive Enterprise...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Dec 29 2009
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