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VHDL,Techfile

  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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