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VHDL-AMS,analog

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • Vhdl-ams beginner

    Hi, I'm really new in vhdl-ams, I write my firsts codes in this langage and I have some issues to understand some basics of this extension. My tutor want me to describe an analogic comparator and test it with a ramp waveform. A schema of this circuit is in attachment. I don't know how to connect...
    Posted to Mixed-Signal Design (Forum) by sebgimi on Tue, Feb 11 2014
  • Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

    Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...
    Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Mon, Aug 27 2012
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