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  • Ultrasim partitioning guidelines

    I have a circuit with multiple 3.3V power domains and multiple 1.8V and 2.4V regulators. Regulator biases come mainly from one bias block on a 3.3V supply.I have defined the regulated output voltages with usim_vr statement. I've also put sim_mode=ms and speed=2 on the regulator blocks themselves...
    Posted to Custom IC Design (Forum) by paulaos on Tue, Jan 19 2010
  • ams: simulating design with spice netlist with bus ports

    I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really...
    Posted to Custom IC Design (Forum) by Runner on Mon, Sep 14 2009
  • UltraSim DC Fail

    I am simulating a parasitic capacitance extracted toplevel circuit with UltraSim 6.0. I have a problem of DC operating point calculation. UltraSim says in output log that "DC simulation finishes without reaching steady state" at the beginning of transient simulation. Then all bias voltages...
    Posted to Custom IC Design (Forum) by OzgurAtes on Mon, Mar 30 2009
  • Ultrasim parasitics spf file format for backannotation

    Hi all. I have some problem with spf files. I want to do post-layout simulation with ultrasim. It is option in ultrasim to supply spf file with extraction information for backannotation. I have spf file I got from StarRCXT(synopsis extraction tool). But when I am trying to do simulation with this file...
    Posted to Custom IC Design (Forum) by Geser on Thu, Feb 19 2009
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