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Ultrasim,ADE

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • $bitstoreal function in IC6.1.5 systemVerilog

    Hi All, I am having the following weird issue: I am trying to do some AMS simulation using IC6.1.5 and ADE. I created a systemVerlog view and used the function "$bitstoreal". When I try to save and close the editor, I get an error: "ncvlog: *E,NOTCMP: unit bitstoreal not found while parsing...
    Posted to Custom IC Design (Forum) by Vijay Srinivas on Thu, Jul 19 2012
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • ams: simulating design with spice netlist with bus ports

    I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really...
    Posted to Custom IC Design (Forum) by Runner on Mon, Sep 14 2009
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