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  • Is Fast SPICE Simulation Hitting a Wall?

    The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed. So-called "Fast SPICE" simulators can provide considerable speedups -- but current Fast SPICE...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 19 2012
  • $bitstoreal function in IC6.1.5 systemVerilog

    Hi All, I am having the following weird issue: I am trying to do some AMS simulation using IC6.1.5 and ADE. I created a systemVerlog view and used the function "$bitstoreal". When I try to save and close the editor, I get an error: "ncvlog: *E,NOTCMP: unit bitstoreal not found while parsing...
    Posted to Custom IC Design (Forum) by Vijay Srinivas on Thu, Jul 19 2012
  • AMS rolling back to the older version of ultrasim

    I am seeing some strange behavior from the AMS simulator. I have changed the MMSIM version to 11.10 to use the most updated ultrasim simulator for multithread simulation. All the environment variables have been updated accordingly. However, when I try to simulate something the log files show that the...
    Posted to Custom IC Design (Forum) by 01farhad10 on Fri, Jun 15 2012
  • multi-Core simulation with Ultrasim?

    I was wondering if it is possible to do multi-Core simulation (multi-threading) with Ultrasim? I looked over the Ultrasim User Guide but I didn't find anything relevant. Thanks
    Posted to Custom IC Design (Forum) by 01farhad10 on Sat, Jun 9 2012
  • How to perform Post-Layout simulations using UltraSim for Black-Box Cells?

    I hope you all are doing fine. I need some guidance regarding post-layout simulation of black-box digital cells from Artisan Standard Cell Library using Ultrasim. We have the verilog, lef and tlf files in the PDK along with CDB symbol database that we converted to OA database. We have imported verilog...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 12 2011
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • Supply current in UltraSim

    Good day. I am trying to simulate a MS design (analog blocks + digital controller) with UltraSim. I care a LOT about accurate estimation of supply current. So this is what I notice: I have an accurate IDD in ANALOG mode (i.e. no partitioning), but scrambled results with MS (and below) modes. Interestingly...
    Posted to Custom IC Design (Forum) by YevgenyP on Fri, Feb 25 2011
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
  • Re: current measure on gnd! global .

    Hi Andrew, Thanks for the answer . Actually i have large design of SRAM's , and i can't sum all current thru hierarchy, and i can't change the name of the net. Do you know any way to get the current of the chip thru gnd! ?
    Posted to Custom IC Design (Forum) by Mike G on Sun, Apr 18 2010
  • current measure on gnd! global .

    Hi, How can i measure total gnd current, the gnd is global net ? thanks
    Posted to Custom IC Design (Forum) by Mike G on Thu, Apr 15 2010
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