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UltraSim,Mixed Signal Design

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • Re: about 64 - 32 bit binaries (ultrasim64)

    Dear Andrew, Thanks for your quick reply. Indeed I cannot run Ultrasim in 64bit mode. Below is the message I get: Connecting to License Server ... Done. Error found by UltraSim. ERROR (USIM-12701): The UltraSim-Verimix (mixed mode) simulator option is not compatible with 64-bit platforms. The UltraSim...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Fri, Jul 5 2013
  • about 64 - 32 bit binaries (ultrasim64)

    Hello, At the tool path "..../MMSIM101/tools/ultrasim/bin" I see the link to executable ultrasim64. However I have to exclude ultrasim from the 64bit tools in order to run (my machine is i5 and tools run on centOS). Is there a way to use 64bit binaries for ultrasim ? Another question: I use...
    Posted to Mixed-Signal Design (Forum) by Thodoros on Wed, Jul 3 2013
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