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UltraSim,ADE XL

  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
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