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UVM,verification,Functional Verification

Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 27 2013
Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 27 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers

The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 24 2013
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 5 2012
Free UVM Tutorial Boosts IC Functional Verification Skills

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled " UVM: Ready, Set, Deploy! " is available through the Accellera Systems...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 12 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...

Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 8 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...

Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal (UVM-MS)

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but the official approval fell between the cracks and didn't come through until recently. Regardless,...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Jul 24 2012

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UVM,verification,Functional Verification

Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

DVCon 2013 Preview – Learn from Other Design and Verification Engineers

EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM

Free UVM Tutorial Boosts IC Functional Verification Skills

UVM Testflow Phases, Reset and Sequences

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal (UVM-MS)