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UVM
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Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance
Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
EE Times Webinar: Verifying ARM ACE Cache-Coherent Interconnects with UVM
Cache-coherent interconnect is a key component of any SoC that uses the ARM AMBA 4 Coherency Extension ( ACE ) specification. It's hard to design and even harder to verify. A recently archived EE Times webinar shows why cache-coherent interconnect is so complex, and explains how to build a Universal...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 5 2012
Mixed-Signal Technology Summit in Japan Provides Technology Updates
Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, Nov 29 2012
Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM
One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more productive. But in order to reduce overall verification...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Nov 28 2012
Cadence Partner Udacity Brings Higher Education to the World
On-line education pioneer Udacity is partnering with Cadence to offer an upcoming free class in functional hardware verification - but Udacity's overall mission is quite a bit broader than that. Says David Evans, vice president of education at Udacity (right): "Our mission is to make high-quality...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 26 2012
UVM e vr_ad -- Specman Read/Write Register Enhancements
If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence 2. Add a field of the type of the register you want to access 3. In the body() , call the read/write_reg For example...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, Nov 23 2012
Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership
A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Oct 19 2012
UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e , SystemVerilog...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Oct 11 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs
In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 9 2012
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