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UVM,Metric-driven verification,Analog
A/MS
Accellera
Advanced Verification Topics
AMS
AMS Designer
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analog assertions
analog behavioral models
analog IP
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Mixed-Signal Technology Summit in Japan Provides Technology Updates
Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Thu, Nov 29 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 29 2012
Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM
Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Mon, Aug 27 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
Free Webinars Explore Advanced Functional Verification Techniques
UVM, assertion-based simulation, metric-driven verification, assertion synthesis, formal scoreboarding -- these are just a few of the advanced techniques that can improve your verification productivity. To help you learn about such techniques, Cadence is offering a series of nine free one-hour webinars...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 15 2011
Hot Topic: Should Separate Teams Handle Analog Verification?
Dedicated verification teams are well established in the digital world, but not in analog/mixed-signal design. Has the time come for separate analog verification teams? I've been following an ongoing debate on this topic in a couple of LinkedIn groups, a debate that followed my recent blog posting...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 21 2011
UVM-MS – Metric-Driven Verification for Analog IP and Mixed-Signal SoCs
Metric-driven verification and constrained-random stimulus generation have greatly eased digital functional verification, but have rarely been applied to analog IP or mixed-signal SoCs. That may change with a proposed methodology called Universal Verification Methodology-Mixed Signal (UVM-MS), which...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 10 2011
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