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DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!
In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, May 1 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 30 2012
UVM: "Everything that Can be Invented Has Been Invented" Not True!
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that...
Posted to
Functional Verification
(Weblog)
by
Adam Sherilog
on Thu, Jan 26 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions
Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 13 2011
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs
If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Mar 6 2011
DVCon Panelists: What Should Accellera Do Next With UVM?
The Universal Verification Methodology (UVM) 1.0 standard has been released by Accellera, but (surprise, surprise) it's not perfect and more needs to be done. What's still missing, and what should Accellera do next? Most panelists and audience members at the DVCon conference March 1 appeared...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 2 2011
Accellera Approves UVM 1.0 – Bold Step Forward for Functional Verification
There's big news today (Feb. 18) in the functional verification world. As noted in various tweets from standards group members, the Accellera standards organization board has unanimously approved the Universal Verification Methodology (UVM) 1.0 as an industry standard for verification interoperability...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Feb 18 2011
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