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TeamFED

  • DesignWare and AmbitWare Demystified - Why and When to Avoid?

    By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
  • Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate

    By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not careful. Such methodology decision can impact: Quality...
    Posted to Logic Design (Weblog) by Team FED on Mon, Jun 22 2009
  • Why Your Project Should Not Follow the Fate of the Mars Orbiter - Part I

    By Diego Hammerschlag Sr. Technical Leader Team FED The “Orbiter” was a spacecraft on a mission to study the planet Mars. Unfortunately, Lockheed Martin and NASA had a mix up using Imperial units (pounds, miles, etc.) and Metric units (kilometers, kilograms, etc.) Bad things happen to spacecraft...
    Posted to Logic Design (Weblog) by Team FED on Mon, May 25 2009
  • Don't Let Power Kill Your Project - What % LVT Should I Use?

    By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
    Posted to Logic Design (Weblog) by Team FED on Wed, May 13 2009
  • How To Improve Timing Critical Path Analysis

    By Jack Marshall Sr. Technical Leader Customer Solutions In my first article I wrote about how to generate a Global Timing Debug (GTD) timing report from within RC which would allow you to send all the necessary information to your favorite Cadence AE to facillitate their debugging of your critical timing...
    Posted to Logic Design (Weblog) by Team FED on Tue, Apr 7 2009
  • Don't Let Power Kill Your Project

    By Diego Hammerschlag Sr. Technical Leader Team FED Power has gone from an imminent threat to the cause of multiple projects across several vendors going under. I have heard of multiple projects that had working RTL prototypes and were far into the backend flow only to find out that the power used would...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 31 2009
  • Where Oh Where is "number_of_routing_layers"?

    OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
    Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009
  • Introducing "Team FED"

    Today we are launching the "Team FED" blog. Similar to some of the other "Team" blogs here at Cadence, this will be focused on technical tips and tricks to help you get the most out of our products and methodologies. In our case, the focus is on Front-End Design, hence the "FED"...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 3 2009
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