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Tcl,clockDesign

  • Virtual Clock and Synthesize :)

    Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...
    Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
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