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TSV,wide i/o,TSMC

  • TSMC 3D-IC Reference Flow Supports 3D Die Stacking

    An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right). While there has been considerable...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 24 2013
  • A New Information Resource for 3D-IC TSV Design

    A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor IP solutions, it includes press releases, blog posts, whitepapers, articles, and an archived webinar...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 16 2012
  • 3D IC Ecosystem Panel: Different Views, Challenging Questions

    The 3D IC supply chain ecosystem is just beginning to emerge, with roles that are currently unclear. So what happens when you bring together representatives from an outsourced assembly and test (OSAT) provider, memory maker, foundry, EDA vendor (Cadence), and a customer? The result: differing perspectives...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 3 2011
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