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  • DAC 2010 – A “Coming Out” Party For 3D-IC Design

    Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system...
    Posted to Digital Implementation (Weblog) by RahulD on Mon, Jun 28 2010
  • 3D IC Standards – First, Let’s Define Our Terms

    There's a lot of interest in 3D ICs these days, but there are many challenges to solve before 3D IC design can move into the mainstream. One challenge is the establishment of standards for design, modeling, and manufacturability. But the starting point is likely to be something even simpler - a dictionary...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 10 2010
  • Favorite Features of an IC Package Designer: Flexible 3D Viewing

    This is the first in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. We talk to customers all the time that are designing IC packages with stacked die. While trough-silicon-via (TSV) is the wave of the future, the vast majority...
    Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Wed, Apr 28 2010
  • EDA Workshop: A Reality Check On 3D ICs

    3D ICs are an attractive technology, but what will it take to make them successful? Presenters at the recent Electronic Design Processes (EDP) workshop didn't have all the answers, but they had a lot of interesting insights into how EDA tools and flows will need to change to support stacked die with...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 19 2010
  • EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

    Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders with the industry's gurus and to discuss...
    Posted to Digital Implementation (Weblog) by RahulD on Fri, Apr 16 2010
  • My DATE With 3DIC Technology

    This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12 th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly?" In fact it did. Last year when I was following...
    Posted to Digital Implementation (Weblog) by samtabansal on Mon, Mar 29 2010
  • Cadence SiP and IC Packaging at DesignCon

    Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology. We will also be showing techniques where Package-on-Package...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Fri, Jan 23 2009
  • CDNLive! - 10 Gbit package design paper available to conference attendees

    For those of you that attended CDNLive! but may have missed the presentation on multi-gigabit package design by Kevin Roselle of Bayside Design, you can review the slide presentation by using your conference login and then downloading from here . Bayside is involved in designing many high-end packages...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Wed, Oct 1 2008
  • TSV, mainstream or niche?

    I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries and some iDM's) talking about pilot projects...
    Posted to IC Packaging and SiP (Weblog) by SiPper on Wed, Sep 24 2008
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