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TSV

14nm
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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
Leverage System Planning to Maximize Performance of Silicon Interposer

Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Thu, Dec 6 2012
Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs

T he recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here . Separately, I interviewed one...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 24 2012
A New Information Resource for 3D-IC TSV Design

A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor IP solutions, it includes press releases, blog posts, whitepapers, articles, and an archived webinar...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 16 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 14 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 21 2012
Panelists: What Needs to Happen for 3D-IC TSV Success

It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 11 2012
EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 10 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs

What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 9 2012

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TSV

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Leverage System Planning to Maximize Performance of Silicon Interposer

Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs

A New Information Resource for 3D-IC TSV Design

DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

Panelists: What Needs to Happen for 3D-IC TSV Success

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

EDA Symposium: Users Cite 3D-IC Design Tool Needs