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TSV,IC Packaging & SiP design

  • Favorite Features of an IC Package Designer: Flexible 3D Viewing

    This is the first in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. We talk to customers all the time that are designing IC packages with stacked die. While trough-silicon-via (TSV) is the wave of the future, the vast majority...
    Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Wed, Apr 28 2010
  • Cadence SiP and IC Packaging at DesignCon

    Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology. We will also be showing techniques where Package-on-Package...
    Posted to IC Packaging and SiP (Weblog) by Maxwell86 on Fri, Jan 23 2009
  • TSV, mainstream or niche?

    I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries and some iDM's) talking about pilot projects...
    Posted to IC Packaging and SiP (Weblog) by SiPper on Wed, Sep 24 2008
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