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TSMC

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 2 2012
Free Webinars Preview 20nm Challenges, Solutions

If you're designing or planning to design at 20nm - or you're just curious about this emerging and much-discussed process node - three free webinars May 1, 2 and 3 will provide a wealth of valuable information. In these webinars, Cadence experts will team up with industry leaders to present 20nm...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 12 2012
CDNLive Silicon Valley 2012: Much More than Moore

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event. Below are some highlights and themes that emerged. Left to right: Keynote speakers Lip-Bu Tan (Cadence...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 20 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs

30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 15 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012
CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

CDNLive! Silicon Valley , the annual Cadence U.S. user conference, opened in San Jose, California March 13, 2012 on an optimistic yet cautionary note. Keynote speakers from Cadence, TSMC and ARM each predicted a new era of innovation in the electronics industry, but also noted daunting challenges that...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 13 2012
TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 2 2012
Video: Why TSMC Cares About System-Level Design

Why would TSMC, the world's largest foundry, care enough about electronic system-level (ESL) design to include it in a reference flow? In the short video clip embedded below, Ashok Mehta, senior manager of system verification and software architecture at TSMC, explains why and how his company worked...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 16 2011
ARM TechCon Address: High Stakes at Low Process Nodes

The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 25 2011
Q&A: Linking Virtual Prototypes to High-Level Synthesis

Virtual prototypes for early software development and high-level synthesis tools for hardware implementation are two important new technologies that are raising the abstraction level in electronic systems design. But these tools are traditionally isolated from one another because they require different...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 29 2011

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TSMC

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

Free Webinars Preview 20nm Challenges, Solutions

CDNLive Silicon Valley 2012: Much More than Moore

CDNLive! Keynote – New Horizons for ARM Based SoCs

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers

TLM: The Year in Review, and Trends for 2012

Video: Why TSMC Cares About System-Level Design

ARM TechCon Address: High Stakes at Low Process Nodes

Q&A: Linking Virtual Prototypes to High-Level Synthesis