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  • Implement TSGEN in IBM 9HP process

    I made several behavioral designs in Verilog that use tri-state buffers. Structural Verilog from Synopsys uses the TSGEN function to implement tri-state buffers, but the tech library does not seem to have TSGEN implemented, and attempting to place & route results in the tri-state outputs being unconnected...
    Posted to Digital Implementation (Forum) by Khenglish on Tue, Jul 8 2014
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