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TLM

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 24 2012
Is System Modeling the Next EDA Abstraction Level?

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 15 2012
Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded systems have a gigabyte or more of SDRAM. For example, one of the Xilinx Zynq boards, known as ZC702, has a Linux Device Tree source file defining the memory size as 0x40000000, or 1 Gb. Thinking about a SystemC model...

Posted to System Design and Verification (Weblog) by jasona on Fri, Apr 13 2012
Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Mar 5 2012
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 27 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Feb 23 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 30 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design

Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 22 2012
TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 2 2012

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TLM

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Is System Modeling the Next EDA Abstraction Level?

Modeling Large Memories in SystemC

Differentiation Through Hardware is Not Going Away

DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards

Virtual Divide and Conquer Enables Fixed Sub-Systems

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

Q&A: Frank Schirrmeister Updates Status of System-Level Design

TLM: The Year in Review, and Trends for 2012