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TLM,System Design and Verification,ESL

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San Francisco and you are interested in SystemC/TLM driven design and verification, including high-level synthesis, there are a lot of interesting sessions. First, there is a parallel conference going on Saturday and Sunday...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, May 31 2012
Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable UART in Virtual Platforms. If you missed the first two parts you can review the introduction and use case 1, about using xterm in slave mode for an interactive terminal . This article explains another way to provide...

Posted to System Design and Verification (Weblog) by jasona on Tue, Sep 6 2011
Creating SystemC TLM-2.0 Peripheral Models

Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time to give you an update, and the good news is that...

Posted to System Design and Verification (Weblog) by TeamESL on Thu, Jul 14 2011
Methodology Is Important But Language Matters - Part 1

Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Jan 26 2010
Verification Productivity Is Holding Back Electronic System Level Development Advances

There is a controversy brewing in our industry, and I'm about to step into it boldly. I don't expect to end the controversy, since it is about the definition of a three letter acronym. And we all know how much the EDA industry likes to create and debate TLAs! The confusion makes it difficult...

Posted to System Design and Verification (Weblog) by Steve Brown on Mon, Nov 30 2009
Synopsys’ “Synphony” Announcement – Welcome to the Party!

I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity boost that'll come from working at a higher...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Wed, Oct 14 2009
SystemC Debug: A Summary of Summary Probes

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in order to represent concurrent systems, whether for...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, May 15 2009
C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C / C++ based ESL tools is its ability to describe multiple concurrent threads. CtoS supports multiple concurrent threads because, rather than using pure C or C++ as input language, CtoS uses SystemC. SystemC and CtoS support...

Posted to System Design and Verification (Weblog) by TeamESL on Wed, Apr 15 2009
C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis tool. The question is usually based on the fact that SystemC is the input language for CtoS. It is partially correct. In reality, CtoS is both a High and a Low level synthesis tool. On the High Level side...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, Apr 3 2009
Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important trends that are driving customers towards system level design and verification. He makes several points about shifts in technology and methodology, and the fact that the RTL remains the golden source even for today's...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Apr 1 2009

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TLM,System Design and Verification,ESL

TLM Design and Verification: What to See at DAC This Year

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Creating SystemC TLM-2.0 Peripheral Models

Methodology Is Important But Language Matters - Part 1

Verification Productivity Is Holding Back Electronic System Level Development Advances

Synopsys’ “Synphony” Announcement – Welcome to the Party!

SystemC Debug: A Summary of Summary Probes

C-to-Silicon Support of Concurrent Processes

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Is ESL changing EDA? Absolutely!