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TLM,MDV,DVCon

  • DVCon Panel: Three Ways To Minimize Verification Effort

    With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three basic approaches to improving verification productivity...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 2 2010
  • DVCon 2010 For The Specmaniac

    At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification technologies and methodologies ( full list of Cadence-sponsored activities is posted here ). Of course, Team Specman is here help Specmaniacs discover the many activities that will feature Specman and e language...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Feb 15 2010
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