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SystemVerilog,sva

2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More

If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Nov 9 2010
Async signal assetions

Hi, There is one async signal a_sync, this signal needs to be stable till first incoming clk. a_sync signal may get change any time irrespective to clk. I have written property as follows, it works fine for single bit, but for multibit a_sync signal I need help. property abc(a_sync, clk); int temp_val;...

Posted to Functional Verification (Forum) by SVA1 on Mon, Aug 3 2009
Profiling the runtime of SystemVerilog Assertions

Hi all, I'm concerned that a collection of assertion based checkers that I'm using are causing a dramatic slow down in the run time of my simulation. My hunch is that the widespread use of multiple internal variables in some of the assertions are using vast amounts of memory and are thus negatively...

Posted to Functional Verification (Forum) by danlarkin on Thu, Jan 15 2009

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SystemVerilog,sva

2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More

Async signal assetions

Profiling the runtime of SystemVerilog Assertions