Home > Community > Tags > SystemVerilog
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

SystemVerilog

  • OVM Innovation Means Business

    Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Tue, Nov 3 2009
  • OVM Tricks and Treats

    Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets! Callback Mechanism...
    Posted to Functional Verification (Weblog) by Team genIES on Fri, Oct 30 2009
  • Why OVM? John Aynsley of Doulos Has 10 Reasons

    Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM. If video fails to play please...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Thu, Oct 22 2009
  • Using Vera is like Speaking Sumerian – Who’s Left to Understand?

    Just like natural languages, non-standard verification languages can fade away. Sure, ancient Sumerian exists in the Code of Hammurabi , but all modern law is written in living languages. Similarly, verification environments and VIP still exist in Vera, but a shrinking population understands and uses...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Sep 30 2009
  • Verification is a Sprint and a Marathon!

    Verification engineers have updated an old adage to discribe their projects: Verification is both a sprint and a marathon! We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between. Cadence answered that comprehensive call in the Performance...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Sep 30 2009
  • CDNLive San Jose 2009 for the Specmaniac

    Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event is a "hybrid" format of in-person workshops and on-line webinars. As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design &...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 30 2009
  • Requirements for a Student Version of Specman/IES-XL?

    Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by the back-to-school season: You may recall a question was posted to Mike Stellfox back in February about the availability of a limited, student version of Specman and IES-XL for the student's personal computer (vs....
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Sep 8 2009
  • Async signal assetions

    Hi, There is one async signal a_sync, this signal needs to be stable till first incoming clk. a_sync signal may get change any time irrespective to clk. I have written property as follows, it works fine for single bit, but for multibit a_sync signal I need help. property abc(a_sync, clk); int temp_val;...
    Posted to Functional Verification (Forum) by SVA1 on Mon, Aug 3 2009
  • FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

    The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today. Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one...
    Posted to Functional Verification (Weblog) by Team genIES on Thu, Jul 23 2009
  • Write Right OVM Verification Components

    The OVM provides the most comprehensive reuse if you follow the methodology it prescribes. While its unique built-in classes are the technical heart of the reuse, you still have to write your own components. Now you have the new Paradigm Works OVC Template Generator to write them in the right way for...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Fri, Jul 17 2009
Page 13 of 16 (157 items) « First ... < Previous 11 12 13 14 15 Next > ... Last »